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Scope -- Submissions -- Key Dates -- Additional Information -- Committee

Scope

The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in testing, debug and repair of microelectronic circuits and systems. Major topics include, but are not limited to:

Analog/Mixed-Signal/RF Test
ATPG & Compression
ATE Architecture & Software
Automotive Test & Safety
Embedded System & Board Test
Embedded Test Methods
Emerging Technologies Test
FPGA Test
Power/Thermal Issues in Test
System-on-Chip (SOC) Test
Test Standards
Test Economics
Built-In Self-Test (BIST)
Defect & Current Based Test
Defect/Fault Tolerance
Delay & Performance Test
Design for Testability (DFT)
Design Verification/Validation
Fault Modeling and Simulation
Hardware Security
Low-Power IC Test
Microsystems/MEMS/Sensors Test
Memory Test and Repair
Test of Biomedical Devices
Test of High-Speed I/O
Test Quality and Reliability
Test Resource Partitioning
Transients and Soft Errors
2.5D, 3D and SiP Test

Submissions

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The VTS Program Committee invites original, unpublished Paper Submissions for VTS 2016. Paper submissions should be complete manuscripts, up to six pages (inclusive of figures, tables, and bibliography) in a standard IEEE two-column format; papers exceeding the page limit will be returned without review. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status. On the title page, please include: author name(s) and affiliation(s), and the mailing address, phone number, and e-mail address of the contact author. A 50- word abstract and five keywords identifying the topic area are also required.

Proposals for the Innovative Practices and Special Sessions tracks are also invited. The innovative practices track highlights cutting-edge challenges faced by test practitioners, and innovative solutions employed to address them. Special sessions can include invited presentations on hot topics, panels, embedded tutorials. Innovative practices and special session track proposals should include a title, name and contact information of the session organizer(s), a 150-to-200 word abstract, and a list of prospective participants.

VTS 2016 will present a Best Paper Award, a Best Special Session Award, and a Best Innovative Practices Session Award based on the evaluations of reviewers, attendees, and an invited panel of judges. We also plan to organize a Student Poster Competition and a TTTC Best Doctoral Thesis Contest, details for which will be available through the VTS website at a later date. The Best Paper of VTS 2015 and the Best Innovative Practices presentation will be invited to resubmit to the IEEE Design & Test of Computers where they will undergo a regular, but expedited, review process.

TTTC Test Technology Educational Program (TTEP) tutorials on emerging test technology topics will be offered in conjunction with VTS 2016. Tutorial proposals should be submitted according to TTEP 2016 submission guidelines, which will be posted on http://computer.org/tab/tttc/teg/ttep

Key Dates

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All submissions are to be made electronically through the VTS website.

The deadline for all submissions is October 16th, 2015. Detailed instructions for submissions will be found at the symposium website http://www.tttc-vts.org.

Authors will be notified of the disposition of their papers by December 20th, 2015.

A submission will be considered as evidence that, upon acceptance, the author(s) will submit a final camera-ready version of the paper for inclusion in the proceedings, and will present the paper at the symposium. A full registration of at least one author is required for publication. In the case of innovative practices and special sessions, the organizers commit to submitting a session title, abstract and list of participants for inclusion in the symposium proceedings.

Additional Information

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For general information:

GENERAL CHAIR

Yiorgos Makris

University of Texas at Dallas

yiorgos.makris@utdallas.edu

For submission-related information:

PROGAM CO-CHAIRS

Lorena Anghel

University of Grenoble-Alpes/TIMA

lorena.anghel@imag.fr

Srivaths Ravi

Texas Instruments

srivaths.ravi@ti.com

Committee

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General Chair:

Y. Makris – University of Texas at Dallas

Program Co-Chairs:

S. Ravi – Texas Instruments
L. Anghel – TIMA Laboratory /University of Grenoble–Alpes

Past Chair:

C. Thibeault – ETS Montreal

Vice-General Chair:

C.H. Chiang – Alcatel-Lucent Vice-Program

Co-Chairs:

R. Kapur – Synopsys
M. Sonza-Reorda – Politecnico di Torino

New Topics:

B. Courtois – CMP
B. Kaminska – Simon Fraser University

Special Sessions:

S. Ozev – Arizona State University
E. Larsson – Lund University

Innovative Practices Track:

A. Majumdar – Xilinx
C. Dixit – Avago

New Initiatives Chair:

S. Mitra – Stanford University
Members:

V. Chickermane – Cadence
Y. Li – University of Chicago

Registration:

J. Dworak – Southern Methodist University

Publications Co-Chairs:

G. Di Natale – LIRMM
Z. Navabi – Worcester Polytechnic
Member:

E. Vatajelu – Politecnico di Torino

Electronic Media Chair:

S. Di Carlo – Politecnico di Torino
Members:

A. Savino – Politecnico di Torino
M. Maniatakos – NYU Abu Dhabi

Finance:

P. Song – IBM

Local Arrangements:

B. Eklow – Cisco

Audio/Visual:

C. Patel – Univ. of Maryland Baltimore County

Corporate Support Chair:

S. Natarajan – Intel
Vice-Chair: B. Cory – Nvidia

Student Activities:

K. Huang – San Diego State University

Publicity Co-Chairs:

O. Sinanoglu – NYU Abu Dhabi J. Carulli – Globalfoundries
Vice-Chair: K. Hatayama – Gunma University

Ex-Officio:

Y. Zorian – Synopsys

Program Committee:

J. Abraham – University of Texas at Austin
V. Agrawal – Auburn University
D. Appello – ST Microelectronics
B. Becker – University of Freiburg
S. Bernard – LIRMM
R. Blanton – Carnegie Melon University
K. Chakrabarty – Duke University
V. Champac – INAOE
A. Chatterjee – Georgia Tech
C. J. Clark – Intellitech
D. Chen – Iowa State University
H. Chen – Mediatek
K. Chung – Samsung
D. Gizopoulos – University of Athens
S. Gupta – University of Southern California
S. Hamdioui – Delft University
I. Hartanto – Xilinx
S. Hellebrand –University of Paderborn
R. Karri – New York University
X. Li – Chinese Academy of Sciences
T.M. Mak – Globalfoundries
S. Makar –
P. Maxwell – ON Semiconductor
S. Mir –TIMA Laboratory
A. Orailoglu – University of California, San Diego
R. Parekhji – Texas Instruments
J. Qian – AMD
J. Rajski – Mentor Graphics
S. Reddy – University of Iowa
M. Renovell – LIRMM
M. Richetti – Synopsys
P. Sarson – ams AG
S. Shaikh – Broadcom
S. Shoukourian – Synopsys
A. Sinha – Intel
M. Slamani – Globalfoundries
H. Stratigopoulos – LIP6
S. Sunter – Mentor Graphics
M. Tahoori – Karlsruhe Institute of Technology
M. Tehranipoor – University of Florida
L. C. Wang – University of California, Santa Barbara
C. W. Wu – NTHU
H.J. Wunderlich – University of Stuttgart

Steering Committee:

M. Abadir – Independent
J. Figueras – Universidad Polytecnic de Catalunya
A. Ivanov – University of British Columbia
M. Nicolaidis – TIMA Laboratory
P. Prinetto – Politecnico di Torino
A. Singh – Auburn University
P. Varma – Ansys
Y. Zorian – Synopsys

For more information, visit us on the web at: http://tttc-vts.org

The 34th IEEE VLSI TEST SYMPOSIUM is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).